NAND flash memories have been developed for high density storage application, such as picture cards for digital cameras, memory of MP players, and universal serial bus (USB) memories. In particular, a cellular phone system and personal digital assistants (PDA) have shown rapid growth to expand its market segment. Further, its application has been extended to PC storage use as a solid-state drive (referred to as an SSD hereinafter), which is an alternative of a hard disk drive (HDD), and is the most promising market domain for the NAND flash memory in the future. However, as the scaling technology for finer pattern in the semiconductor memories is further developed, the NAND flash memories face such a physical limitation as in terms of the cell operability, where the narrow threshold voltage (Vth) windows become, in particular, a serious issue for multi-level cell (MLC) operation. The threshold voltage of a MOS transistor is referred to as a Vth voltage hereinafter.
In pursuing high-density storage and higher performance in data reliability for NAND flash memory, programming disturb is one of the most critical issues, and the capacitance coupling interference between neighboring floating gates is also critical. These factors broaden the Vth distribution and decrease the Vth windows for the MLC operation. Such programming disturb is also critical issue for a single level cell (SLC) to cause failure in a multiple overwrite operation in one page or at non-sequential data programming from source line SL side to bit line BL side.